set_property -dict {PACKAGE_PIN G12 IOSTANDARD LVCMOS18} [get_ports sys_rst_i]
set_property -dict {PACKAGE_PIN C8 IOSTANDARD DIFF_SSTL135} [get_ports sys_clk_p]
set_property -dict {PACKAGE_PIN K13 IOSTANDARD LVCMOS18} [get_ports clk_out]

set_property IOSTANDARD LVCMOS18 [get_ports pcie_rst_n]
set_property PULLUP true [get_ports pcie_rst_n]
set_property PACKAGE_PIN F13 [get_ports pcie_rst_n]

set_property PACKAGE_PIN R6 [get_ports {pcie_ref_clk_p[0]}]

#set_property LOC GTXE2_CHANNEL_X0Y12 [get_cells {pcie_system_wrapper/pcie_system_i/xdma_0/inst/pcie_system_xdma_0_0_pcie2_to_pcie3_wrapper_i/pcie2_ip_i/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/gtx_channel.gtxe2_channel_i}]
set_property LOC GTXE2_CHANNEL_X0Y12 [get_cells {pcie_system_wrapper/pcie_system_i/PCIE_SYS/xdma_0/inst/pcie_system_xdma_0_0_pcie2_to_pcie3_wrapper_i/pcie2_ip_i/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/gtx_channel.gtxe2_channel_i}]
set_property PACKAGE_PIN AB4 [get_ports {pcie_mgt_rxp[3]}]
set_property PACKAGE_PIN AA2 [get_ports {pcie_mgt_txp[3]}]

#set_property LOC GTXE2_CHANNEL_X0Y13 [get_cells {pcie_system_wrapper/pcie_system_i/xdma_0/inst/pcie_system_xdma_0_0_pcie2_to_pcie3_wrapper_i/pcie2_ip_i/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/gtx_channel.gtxe2_channel_i}]
set_property LOC GTXE2_CHANNEL_X0Y13 [get_cells {pcie_system_wrapper/pcie_system_i/PCIE_SYS/xdma_0/inst/pcie_system_xdma_0_0_pcie2_to_pcie3_wrapper_i/pcie2_ip_i/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/gtx_channel.gtxe2_channel_i}]
set_property PACKAGE_PIN Y4 [get_ports {pcie_mgt_rxp[2]}]
set_property PACKAGE_PIN W2 [get_ports {pcie_mgt_txp[2]}]

#set_property LOC GTXE2_CHANNEL_X0Y14 [get_cells {pcie_system_wrapper/pcie_system_i/xdma_0/inst/pcie_system_xdma_0_0_pcie2_to_pcie3_wrapper_i/pcie2_ip_i/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/gtx_channel.gtxe2_channel_i}]
set_property LOC GTXE2_CHANNEL_X0Y14 [get_cells {pcie_system_wrapper/pcie_system_i/PCIE_SYS/xdma_0/inst/pcie_system_xdma_0_0_pcie2_to_pcie3_wrapper_i/pcie2_ip_i/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/gtx_channel.gtxe2_channel_i}]
set_property PACKAGE_PIN V4 [get_ports {pcie_mgt_rxp[1]}]
set_property PACKAGE_PIN U2 [get_ports {pcie_mgt_txp[1]}]

#set_property LOC GTXE2_CHANNEL_X0Y15 [get_cells {pcie_system_wrapper/pcie_system_i/xdma_0/inst/pcie_system_xdma_0_0_pcie2_to_pcie3_wrapper_i/pcie2_ip_i/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gtx_channel.gtxe2_channel_i}]
set_property LOC GTXE2_CHANNEL_X0Y15 [get_cells {pcie_system_wrapper/pcie_system_i/PCIE_SYS/xdma_0/inst/pcie_system_xdma_0_0_pcie2_to_pcie3_wrapper_i/pcie2_ip_i/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gtx_channel.gtxe2_channel_i}]
set_property PACKAGE_PIN T4 [get_ports {pcie_mgt_rxp[0]}]
set_property PACKAGE_PIN R2 [get_ports {pcie_mgt_txp[0]}]
#�ſ��ź�
#set_property PACKAGE_PIN G15 [get_ports validref]
#set_property IOSTANDARD LVCMOS18 [get_ports validref]
#set_property PACKAGE_PIN G14 [get_ports SwitchOutput]
#set_property IOSTANDARD LVCMOS18 [get_ports SwitchOutput]
#set_property PACKAGE_PIN G16 [get_ports rx1_dat]
#set_property PACKAGE_PIN J15 [get_ports tx1_dat]
#set_property IOSTANDARD LVCMOS18 [get_ports rx1_dat]
#set_property IOSTANDARD LVCMOS18 [get_ports tx1_dat]

set_property PACKAGE_PIN K15 [get_ports i_pps]
#set_property PACKAGE_PIN J13 [get_ports o_rd_int]
set_property IOSTANDARD LVCMOS18 [get_ports i_pps]
#set_property IOSTANDARD LVCMOS18 [get_ports o_rd_int]




#led0~led3
set_property -dict {PACKAGE_PIN G10 IOSTANDARD LVCMOS18} [get_ports {led[0]}]
set_property -dict {PACKAGE_PIN F10 IOSTANDARD LVCMOS18} [get_ports {led[1]}]
set_property -dict {PACKAGE_PIN E11 IOSTANDARD LVCMOS18} [get_ports {led[2]}]
set_property -dict {PACKAGE_PIN D11 IOSTANDARD LVCMOS18} [get_ports {led[3]}]

#TP
#set_property -dict {PACKAGE_PIN E13 IOSTANDARD LVCMOS18} [get_ports pulse_o]
set_property -dict {PACKAGE_PIN H13 IOSTANDARD LVCMOS18} [get_ports iic_scl]
set_property -dict {PACKAGE_PIN H12 IOSTANDARD LVCMOS18} [get_ports iic_sda]

set_property -dict {PACKAGE_PIN AB25 IOSTANDARD LVCMOS25} [get_ports tx1_b_hmc624_spi_cs]
set_property -dict {PACKAGE_PIN AA24 IOSTANDARD LVCMOS25} [get_ports tx1_hmc624_spi_cs]
set_property -dict {PACKAGE_PIN AE25 IOSTANDARD LVCMOS25} [get_ports tx1_hmc624_spi_clk]
set_property -dict {PACKAGE_PIN AE26 IOSTANDARD LVCMOS25} [get_ports tx1_hmc624_spi_data]

set_property -dict {PACKAGE_PIN W15 IOSTANDARD LVCMOS25} [get_ports rx1_b_hmc624_spi_cs]
set_property -dict {PACKAGE_PIN AB26 IOSTANDARD LVCMOS25} [get_ports rx1_hmc624_spi_cs]
set_property -dict {PACKAGE_PIN AD25 IOSTANDARD LVCMOS25} [get_ports rx1_hmc624_spi_clk]
set_property -dict {PACKAGE_PIN AD26 IOSTANDARD LVCMOS25} [get_ports rx1_hmc624_spi_data]

#TimeSync_PPS by fcm, G14 is clock pin
set_property PACKAGE_PIN G15 [get_ports PPS1]
set_property PACKAGE_PIN G14 [get_ports PPS2]
set_property IOSTANDARD LVCMOS18 [get_ports PPS1]
set_property IOSTANDARD LVCMOS18 [get_ports PPS2]
#set_property SLEW <FAST> [get_ports PPS1]
#set_property SLEW <FAST> [get_ports PPS2]

# LED
set_property PACKAGE_PIN J13 [get_ports LED_system]
set_property PACKAGE_PIN G16 [get_ports LED_master]
set_property PACKAGE_PIN J15 [get_ports LED_slave]
set_property PACKAGE_PIN E13 [get_ports LED_sync]
set_property IOSTANDARD LVCMOS18 [get_ports LED_system]
set_property IOSTANDARD LVCMOS18 [get_ports LED_master]
set_property IOSTANDARD LVCMOS18 [get_ports LED_slave]
set_property IOSTANDARD LVCMOS18 [get_ports LED_sync]

create_clock -period 5.000 -name sys_clk [get_ports sys_clk_p]

create_clock -period 10.000 -name pcie_ref -waveform {0.000 5.000} [get_ports {pcie_ref_clk_p[0]}]




######################
#----------

# clocks

create_clock -period 8.000 -name rx_0_clk [get_ports rx_clk_in_0_p]
create_clock -period 8.000 -name rx_1_clk [get_ports rx_clk_in_1_p]
create_clock -period 8.000 -name spi0_clk [get_pins -hier */EMIOSPI0SCLKO]

create_generated_clock -name ad9361_0_clkin -source [get_ports rx_clk_in_0_p] -divide_by 1 [get_pins pcie_system_wrapper/pcie_system_i/axi_ad9361_0/clk]
create_generated_clock -name ad9361_1_clkin -source [get_ports rx_clk_in_0_p] -divide_by 1 [get_pins pcie_system_wrapper/pcie_system_i/axi_ad9361_1/clk]


create_generated_clock -name ad9361_0_dclk -source [get_pins pcie_system_wrapper/pcie_system_i/PS_IP/processing_system7_0/FCLK_CLK1] -divide_by 1 [get_pins pcie_system_wrapper/pcie_system_i/axi_ad9361_0/delay_clk]
create_generated_clock -name ad9361_1_dclk -source [get_pins pcie_system_wrapper/pcie_system_i/PS_IP/processing_system7_0/FCLK_CLK1] -divide_by 1 [get_pins pcie_system_wrapper/pcie_system_i/axi_ad9361_1/delay_clk]

create_generated_clock -name iclk_div_2 -source [get_pins pcie_system_wrapper/pcie_system_i/util_ad9361_divclk/inst/clk_divide_sel_1/O] -divide_by 1 [get_pins pcie_system_wrapper/pcie_system_i/util_ad9361_divclk/clk_out]




#############






connect_debug_port u_ila_0/probe0 [get_nets [list {pcie_lite_map/bramctrl_addr[0]} {pcie_lite_map/bramctrl_addr[1]} {pcie_lite_map/bramctrl_addr[2]} {pcie_lite_map/bramctrl_addr[3]} {pcie_lite_map/bramctrl_addr[4]} {pcie_lite_map/bramctrl_addr[5]} {pcie_lite_map/bramctrl_addr[6]} {pcie_lite_map/bramctrl_addr[7]} {pcie_lite_map/bramctrl_addr[8]} {pcie_lite_map/bramctrl_addr[9]} {pcie_lite_map/bramctrl_addr[10]} {pcie_lite_map/bramctrl_addr[11]} {pcie_lite_map/bramctrl_addr[12]}]]
connect_debug_port u_ila_0/probe1 [get_nets [list {pcie_lite_map/bramctrl_we[0]} {pcie_lite_map/bramctrl_we[1]} {pcie_lite_map/bramctrl_we[2]} {pcie_lite_map/bramctrl_we[3]}]]
connect_debug_port u_ila_0/probe2 [get_nets [list {pcie_lite_map/seg_need_read_Delay_cnt[0]} {pcie_lite_map/seg_need_read_Delay_cnt[1]} {pcie_lite_map/seg_need_read_Delay_cnt[2]} {pcie_lite_map/seg_need_read_Delay_cnt[3]} {pcie_lite_map/seg_need_read_Delay_cnt[4]} {pcie_lite_map/seg_need_read_Delay_cnt[5]} {pcie_lite_map/seg_need_read_Delay_cnt[6]} {pcie_lite_map/seg_need_read_Delay_cnt[7]} {pcie_lite_map/seg_need_read_Delay_cnt[8]} {pcie_lite_map/seg_need_read_Delay_cnt[9]} {pcie_lite_map/seg_need_read_Delay_cnt[10]} {pcie_lite_map/seg_need_read_Delay_cnt[11]} {pcie_lite_map/seg_need_read_Delay_cnt[12]} {pcie_lite_map/seg_need_read_Delay_cnt[13]} {pcie_lite_map/seg_need_read_Delay_cnt[14]} {pcie_lite_map/seg_need_read_Delay_cnt[15]} {pcie_lite_map/seg_need_read_Delay_cnt[16]} {pcie_lite_map/seg_need_read_Delay_cnt[17]} {pcie_lite_map/seg_need_read_Delay_cnt[18]} {pcie_lite_map/seg_need_read_Delay_cnt[19]} {pcie_lite_map/seg_need_read_Delay_cnt[20]} {pcie_lite_map/seg_need_read_Delay_cnt[21]} {pcie_lite_map/seg_need_read_Delay_cnt[22]} {pcie_lite_map/seg_need_read_Delay_cnt[23]} {pcie_lite_map/seg_need_read_Delay_cnt[24]} {pcie_lite_map/seg_need_read_Delay_cnt[25]} {pcie_lite_map/seg_need_read_Delay_cnt[26]} {pcie_lite_map/seg_need_read_Delay_cnt[27]} {pcie_lite_map/seg_need_read_Delay_cnt[28]} {pcie_lite_map/seg_need_read_Delay_cnt[29]} {pcie_lite_map/seg_need_read_Delay_cnt[30]} {pcie_lite_map/seg_need_read_Delay_cnt[31]}]]
connect_debug_port u_ila_0/probe4 [get_nets [list {pcie_lite_map/seg_need_read_GNSS_PPS[0]} {pcie_lite_map/seg_need_read_GNSS_PPS[1]} {pcie_lite_map/seg_need_read_GNSS_PPS[2]} {pcie_lite_map/seg_need_read_GNSS_PPS[3]} {pcie_lite_map/seg_need_read_GNSS_PPS[4]} {pcie_lite_map/seg_need_read_GNSS_PPS[5]} {pcie_lite_map/seg_need_read_GNSS_PPS[6]} {pcie_lite_map/seg_need_read_GNSS_PPS[7]} {pcie_lite_map/seg_need_read_GNSS_PPS[8]} {pcie_lite_map/seg_need_read_GNSS_PPS[9]} {pcie_lite_map/seg_need_read_GNSS_PPS[10]} {pcie_lite_map/seg_need_read_GNSS_PPS[11]} {pcie_lite_map/seg_need_read_GNSS_PPS[12]} {pcie_lite_map/seg_need_read_GNSS_PPS[13]} {pcie_lite_map/seg_need_read_GNSS_PPS[14]} {pcie_lite_map/seg_need_read_GNSS_PPS[15]} {pcie_lite_map/seg_need_read_GNSS_PPS[16]} {pcie_lite_map/seg_need_read_GNSS_PPS[17]} {pcie_lite_map/seg_need_read_GNSS_PPS[18]} {pcie_lite_map/seg_need_read_GNSS_PPS[19]} {pcie_lite_map/seg_need_read_GNSS_PPS[20]} {pcie_lite_map/seg_need_read_GNSS_PPS[21]} {pcie_lite_map/seg_need_read_GNSS_PPS[22]} {pcie_lite_map/seg_need_read_GNSS_PPS[23]} {pcie_lite_map/seg_need_read_GNSS_PPS[24]} {pcie_lite_map/seg_need_read_GNSS_PPS[25]} {pcie_lite_map/seg_need_read_GNSS_PPS[26]} {pcie_lite_map/seg_need_read_GNSS_PPS[27]} {pcie_lite_map/seg_need_read_GNSS_PPS[28]} {pcie_lite_map/seg_need_read_GNSS_PPS[29]} {pcie_lite_map/seg_need_read_GNSS_PPS[30]} {pcie_lite_map/seg_need_read_GNSS_PPS[31]}]]
connect_debug_port u_ila_0/probe6 [get_nets [list {pcie_lite_map/bramctrl_data_out[0]} {pcie_lite_map/bramctrl_data_out[1]} {pcie_lite_map/bramctrl_data_out[2]} {pcie_lite_map/bramctrl_data_out[3]} {pcie_lite_map/bramctrl_data_out[4]} {pcie_lite_map/bramctrl_data_out[5]} {pcie_lite_map/bramctrl_data_out[6]} {pcie_lite_map/bramctrl_data_out[7]} {pcie_lite_map/bramctrl_data_out[8]} {pcie_lite_map/bramctrl_data_out[9]} {pcie_lite_map/bramctrl_data_out[10]} {pcie_lite_map/bramctrl_data_out[11]} {pcie_lite_map/bramctrl_data_out[12]} {pcie_lite_map/bramctrl_data_out[13]} {pcie_lite_map/bramctrl_data_out[14]} {pcie_lite_map/bramctrl_data_out[15]} {pcie_lite_map/bramctrl_data_out[16]} {pcie_lite_map/bramctrl_data_out[17]} {pcie_lite_map/bramctrl_data_out[18]} {pcie_lite_map/bramctrl_data_out[19]} {pcie_lite_map/bramctrl_data_out[20]} {pcie_lite_map/bramctrl_data_out[21]} {pcie_lite_map/bramctrl_data_out[22]} {pcie_lite_map/bramctrl_data_out[23]} {pcie_lite_map/bramctrl_data_out[24]} {pcie_lite_map/bramctrl_data_out[25]} {pcie_lite_map/bramctrl_data_out[26]} {pcie_lite_map/bramctrl_data_out[27]} {pcie_lite_map/bramctrl_data_out[28]} {pcie_lite_map/bramctrl_data_out[29]} {pcie_lite_map/bramctrl_data_out[30]} {pcie_lite_map/bramctrl_data_out[31]}]]
connect_debug_port u_ila_0/probe7 [get_nets [list {pcie_lite_map/PPS_control_back[0]} {pcie_lite_map/PPS_control_back[1]} {pcie_lite_map/PPS_control_back[2]} {pcie_lite_map/PPS_control_back[3]} {pcie_lite_map/PPS_control_back[4]} {pcie_lite_map/PPS_control_back[5]} {pcie_lite_map/PPS_control_back[6]} {pcie_lite_map/PPS_control_back[7]} {pcie_lite_map/PPS_control_back[8]} {pcie_lite_map/PPS_control_back[9]} {pcie_lite_map/PPS_control_back[10]} {pcie_lite_map/PPS_control_back[11]} {pcie_lite_map/PPS_control_back[12]} {pcie_lite_map/PPS_control_back[13]} {pcie_lite_map/PPS_control_back[14]} {pcie_lite_map/PPS_control_back[15]} {pcie_lite_map/PPS_control_back[16]} {pcie_lite_map/PPS_control_back[17]} {pcie_lite_map/PPS_control_back[18]} {pcie_lite_map/PPS_control_back[19]} {pcie_lite_map/PPS_control_back[20]} {pcie_lite_map/PPS_control_back[21]} {pcie_lite_map/PPS_control_back[22]} {pcie_lite_map/PPS_control_back[23]} {pcie_lite_map/PPS_control_back[24]} {pcie_lite_map/PPS_control_back[25]} {pcie_lite_map/PPS_control_back[26]} {pcie_lite_map/PPS_control_back[27]} {pcie_lite_map/PPS_control_back[28]} {pcie_lite_map/PPS_control_back[29]} {pcie_lite_map/PPS_control_back[30]} {pcie_lite_map/PPS_control_back[31]}]]
connect_debug_port u_ila_0/probe8 [get_nets [list {pcie_lite_map/TestRegOut[0]} {pcie_lite_map/TestRegOut[1]} {pcie_lite_map/TestRegOut[2]} {pcie_lite_map/TestRegOut[3]} {pcie_lite_map/TestRegOut[4]} {pcie_lite_map/TestRegOut[5]} {pcie_lite_map/TestRegOut[6]} {pcie_lite_map/TestRegOut[7]} {pcie_lite_map/TestRegOut[8]} {pcie_lite_map/TestRegOut[9]} {pcie_lite_map/TestRegOut[10]} {pcie_lite_map/TestRegOut[11]} {pcie_lite_map/TestRegOut[12]} {pcie_lite_map/TestRegOut[13]} {pcie_lite_map/TestRegOut[14]} {pcie_lite_map/TestRegOut[15]} {pcie_lite_map/TestRegOut[16]} {pcie_lite_map/TestRegOut[17]} {pcie_lite_map/TestRegOut[18]} {pcie_lite_map/TestRegOut[19]} {pcie_lite_map/TestRegOut[20]} {pcie_lite_map/TestRegOut[21]} {pcie_lite_map/TestRegOut[22]} {pcie_lite_map/TestRegOut[23]} {pcie_lite_map/TestRegOut[24]} {pcie_lite_map/TestRegOut[25]} {pcie_lite_map/TestRegOut[26]} {pcie_lite_map/TestRegOut[27]} {pcie_lite_map/TestRegOut[28]} {pcie_lite_map/TestRegOut[29]} {pcie_lite_map/TestRegOut[30]} {pcie_lite_map/TestRegOut[31]}]]
connect_debug_port u_ila_0/probe9 [get_nets [list {pcie_lite_map/bramctrl_data_in[0]} {pcie_lite_map/bramctrl_data_in[1]} {pcie_lite_map/bramctrl_data_in[2]} {pcie_lite_map/bramctrl_data_in[3]} {pcie_lite_map/bramctrl_data_in[4]} {pcie_lite_map/bramctrl_data_in[5]} {pcie_lite_map/bramctrl_data_in[6]} {pcie_lite_map/bramctrl_data_in[7]} {pcie_lite_map/bramctrl_data_in[8]} {pcie_lite_map/bramctrl_data_in[9]} {pcie_lite_map/bramctrl_data_in[10]} {pcie_lite_map/bramctrl_data_in[11]} {pcie_lite_map/bramctrl_data_in[12]} {pcie_lite_map/bramctrl_data_in[13]} {pcie_lite_map/bramctrl_data_in[14]} {pcie_lite_map/bramctrl_data_in[15]} {pcie_lite_map/bramctrl_data_in[16]} {pcie_lite_map/bramctrl_data_in[17]} {pcie_lite_map/bramctrl_data_in[18]} {pcie_lite_map/bramctrl_data_in[19]} {pcie_lite_map/bramctrl_data_in[20]} {pcie_lite_map/bramctrl_data_in[21]} {pcie_lite_map/bramctrl_data_in[22]} {pcie_lite_map/bramctrl_data_in[23]} {pcie_lite_map/bramctrl_data_in[24]} {pcie_lite_map/bramctrl_data_in[25]} {pcie_lite_map/bramctrl_data_in[26]} {pcie_lite_map/bramctrl_data_in[27]} {pcie_lite_map/bramctrl_data_in[28]} {pcie_lite_map/bramctrl_data_in[29]} {pcie_lite_map/bramctrl_data_in[30]} {pcie_lite_map/bramctrl_data_in[31]}]]
connect_debug_port u_ila_0/probe13 [get_nets [list pcie_lite_map/bramctrl_en]]

create_debug_core u_ila_0 ila
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
set_property port_width 1 [get_debug_ports u_ila_0/clk]
connect_debug_port u_ila_0/clk [get_nets [list Clk_Dif2Sig/o_clk]]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
set_property port_width 32 [get_debug_ports u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets [list {TimeSync_inst/Integer_cycle[0]} {TimeSync_inst/Integer_cycle[1]} {TimeSync_inst/Integer_cycle[2]} {TimeSync_inst/Integer_cycle[3]} {TimeSync_inst/Integer_cycle[4]} {TimeSync_inst/Integer_cycle[5]} {TimeSync_inst/Integer_cycle[6]} {TimeSync_inst/Integer_cycle[7]} {TimeSync_inst/Integer_cycle[8]} {TimeSync_inst/Integer_cycle[9]} {TimeSync_inst/Integer_cycle[10]} {TimeSync_inst/Integer_cycle[11]} {TimeSync_inst/Integer_cycle[12]} {TimeSync_inst/Integer_cycle[13]} {TimeSync_inst/Integer_cycle[14]} {TimeSync_inst/Integer_cycle[15]} {TimeSync_inst/Integer_cycle[16]} {TimeSync_inst/Integer_cycle[17]} {TimeSync_inst/Integer_cycle[18]} {TimeSync_inst/Integer_cycle[19]} {TimeSync_inst/Integer_cycle[20]} {TimeSync_inst/Integer_cycle[21]} {TimeSync_inst/Integer_cycle[22]} {TimeSync_inst/Integer_cycle[23]} {TimeSync_inst/Integer_cycle[24]} {TimeSync_inst/Integer_cycle[25]} {TimeSync_inst/Integer_cycle[26]} {TimeSync_inst/Integer_cycle[27]} {TimeSync_inst/Integer_cycle[28]} {TimeSync_inst/Integer_cycle[29]} {TimeSync_inst/Integer_cycle[30]} {TimeSync_inst/Integer_cycle[31]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
set_property port_width 32 [get_debug_ports u_ila_0/probe1]
connect_debug_port u_ila_0/probe1 [get_nets [list {TimeSync_inst/cnt2[0]} {TimeSync_inst/cnt2[1]} {TimeSync_inst/cnt2[2]} {TimeSync_inst/cnt2[3]} {TimeSync_inst/cnt2[4]} {TimeSync_inst/cnt2[5]} {TimeSync_inst/cnt2[6]} {TimeSync_inst/cnt2[7]} {TimeSync_inst/cnt2[8]} {TimeSync_inst/cnt2[9]} {TimeSync_inst/cnt2[10]} {TimeSync_inst/cnt2[11]} {TimeSync_inst/cnt2[12]} {TimeSync_inst/cnt2[13]} {TimeSync_inst/cnt2[14]} {TimeSync_inst/cnt2[15]} {TimeSync_inst/cnt2[16]} {TimeSync_inst/cnt2[17]} {TimeSync_inst/cnt2[18]} {TimeSync_inst/cnt2[19]} {TimeSync_inst/cnt2[20]} {TimeSync_inst/cnt2[21]} {TimeSync_inst/cnt2[22]} {TimeSync_inst/cnt2[23]} {TimeSync_inst/cnt2[24]} {TimeSync_inst/cnt2[25]} {TimeSync_inst/cnt2[26]} {TimeSync_inst/cnt2[27]} {TimeSync_inst/cnt2[28]} {TimeSync_inst/cnt2[29]} {TimeSync_inst/cnt2[30]} {TimeSync_inst/cnt2[31]}]]
create_debug_port u_ila_0 probe
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
set_property port_width 12 [get_debug_ports u_ila_0/probe2]
connect_debug_port u_ila_0/probe2 [get_nets [list {TimeSync_inst/VCO_Phase[0]} {TimeSync_inst/VCO_Phase[1]} {TimeSync_inst/VCO_Phase[2]} {TimeSync_inst/VCO_Phase[3]} {TimeSync_inst/VCO_Phase[4]} {TimeSync_inst/VCO_Phase[5]} {TimeSync_inst/VCO_Phase[6]} {TimeSync_inst/VCO_Phase[7]} {TimeSync_inst/VCO_Phase[8]} {TimeSync_inst/VCO_Phase[9]} {TimeSync_inst/VCO_Phase[10]} {TimeSync_inst/VCO_Phase[11]}]]
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets clk_out_OBUF]
